Reliability analysis of combinational circuits based on a probabilistic binomial model

Reliability analysis of digital circuits is becoming an important feature in the design process of nanoscale systems. Understanding the relations between circuit structure and its reliability allows the designer to implement some tradeoffs that can improve the resulting design. This work presents a probabilistic model that computes the reliability of combinational logic circuits relating to single and multiple faults. The methodology is targeted (but not limited) to circuits generated by synthesis tools, and standard cell based implementation. To validate the proposed methodology we have studied the reliability of some adder structures. Complexity and scalability of the model are discussed and some optimizations are presented.