Thermo-structural behavior of underfilled flip-chips

The continuing drive towards high-density, low-profile integrated circuit packaging has accelerated the spread of flip-chip technology. The use of an area array of solder bumps for the electrical and mechanical, as well as thermal attachment of the chip to the substrate provides flip-chip technology with considerable advantages in cost, density, and electrical performance, relative to the use of conventional single-chip packages. Unfortunately, however the difference in the coefficients of thermal expansion, between the silicon die and the substrate, leads to substantial, thermally-induced strains, which can result in fatigue failure of the solder joints. This problem is exacerbated by the use of the larger chips now becoming available. In recent years it has been found possible to obtain dramatically-higher reliability and to operate successfully with much larger chip sizes by “underfilling” the gap between the chip and substrate with epoxy. The present effort is aimed at exploring the thermo-structural behavior of such underfilled chips and more firmly establishing the physical basis for the improved reliability of this packaging technology. The thermo-structural behavior of an underfilled flip-chip package has been evaluated using the structural FEM code NIKEDP and employing an axisymmetric model of a typical flip-chip structure. In the course of this effort, numerical simulations were performed for underfill materials of varying thermo-structural properties and two solder bump heights. The results were used to examine the parametric sensitivity of the thermal strain in the solder joints and the axial, as well as shear, stress in the underfill material. The Coffin-Manson relation is used to relate the increased number of cycles-to-failure to the solder strain reduction associated with the use of underfilling