• DocumentCode
    2680511
  • Title

    Bottom leaded plastic (BLP) package: a new design with enhanced solder joint reliability

  • Author

    Kim, Young-Gon ; Han, Bongtae ; Choi, Shin ; Kim, Myung-Ki

  • Author_Institution
    LG Semicon Package R&D Center, Cheong-Ju, South Korea
  • fYear
    1996
  • fDate
    28-31 May 1996
  • Firstpage
    448
  • Lastpage
    452
  • Abstract
    The ultra-thin and crack free bottom leaded plastic (BLP) package has been developed by LG Semicon mainly for memory devices. The package can be manufactured by the conventional plastic package manufacturing process with an appropriate modification. The BLP package has no lateral leads and this novel leadless design concept provides numerous advantages over the conventional packages. They include: (1) compactness and low profile, (2) higher electrical performance and (3) enhanced thermal performance [2]. These advantages made the current design of the BLP package an optimal choice for many applications. In order to extend its applicability into high-end memory devices, however, the improvement of solder joint reliability of the current BLP package assembly becomes increasingly important. In this paper, an improved design of the BLP package is proposed to enhance the solder joint reliability. Solder joint strains of the current and the proposed designs are evaluated by an experimentally verified 3-D FEM model. The results are used to assess relative reliability of the proposed design. The relative reliability is estimated by the average shear strain of the solder joint, based on the modified Coffin-Manson relationship. The analysis indicates that the proposed design enhances the solder joint reliability nearly three times, compared to the current design. More applications are anticipated with the improved design
  • Keywords
    finite element analysis; integrated circuit design; integrated circuit packaging; integrated circuit reliability; integrated memory circuits; plastic packaging; 3D FEM model; average shear strain; bottom leaded plastic package; electrical performance; joint strains; leadless design concept; memory devices; profile; solder joint reliability; thermal performance; Assembly; Capacitive sensors; Chip scale packaging; Electronic packaging thermal management; Electronics packaging; Lead; Manufacturing processes; Plastic packaging; Soldering; Thermal expansion;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components and Technology Conference, 1996. Proceedings., 46th
  • Conference_Location
    Orlando, FL
  • ISSN
    0569-5503
  • Print_ISBN
    0-7803-3286-5
  • Type

    conf

  • DOI
    10.1109/ECTC.1996.517425
  • Filename
    517425