Low-power multiple-bit upset tolerant memory optimization

In this paper, we propose a framework for analyzing Soft Error Rates (SER) including Multiple-Bit Upsets (MBU). Then, using this framework, we optimize the soft error tolerant voltage (V_tol) and interleaving distance (ID) of low-power, error-tolerant memories. Experimental results show that the total power can be reduced by an average of 30.5% with V_tol optimization and an average of 40.9% by simultaneously considering V_tol and ID together when compared to worst-case design practices.