A statistical application model for fast MPSoC simulation

Nowadays, integration of a large number of processors on the same silicon die has become technically possible; however these multiprocessor system-on-chips (MPSoC) require new design methodologies, and therefore design space exploration (DSE) methods should be utilized. Also, these new methods should deal with problems like deep submicron effects and design complexities on one hand, and meet the time-to-market requirements on the other hand; hence they usually experience a tradeoff between precision of results and the exploration time. In this paper, we present a statistical application model in order to speed up the MPSoC design space exploration process. We also introduce our exploration tool, developed based on this model, and present the simulation results to prove its correctness.