A method of unsensitizable path identification using high level design information

This paper proposes a method of unsensitizable path identification. By dealing with untestable paths in sequential circuits at register-transfer level (RTL) and utilizing design information obtained from high-level synthesis, the method can identify sequentially unsensitizable paths effectively and efficiently. Information about identified unsensitizable paths can not only facilitate process of test generation but also mitigate futileness of testing. In this work, we employ non-robust unsensitizability, which is widely supported in current ATPG systems, for identifying unsensitizable paths. We show the effectiveness of use of high-level design information through our experiments using RTL circuits synthesized from behavioral benchmark circuits.