A BIST architecture for sigma delta ADC testing based on embedded NOEB Self-Test and CORDIC algorithm

This paper presents a Built In Self Test (BIST) technique for sigma delta ADC testing. The proposed solution consists in a mostly digital module, using a binary stream as test stimulus and sine wave fitting algorithm to estimate Signal-to-Noise and Distortion Ratio. Reference signal is generated using COordinate Rotation DIgital Computer CORDIC algorithm. The same structure is used for offset and amplitude adjustment. We are targeting a significant area overhead reduction by proposing a modified Number of Effective Bits NOEB estimation approach, based upon the absolute sum values rather than sum square values. This technique avoids the use of heavy digital signal processing, since it is based on multiplication and division operations. The architecture is completely described at RTL level and does not depend on the ADC features. Experimental results show the efficiency of our approach to test the sigma delta ADC.