DocumentCode
2683201
Title
Design trade-offs in high performance packages
Author
Kadakia, Suresh D. ; Agrawal, Amit P.
Author_Institution
IBM Corp., Hopewell Junction, NY, USA
fYear
1996
fDate
28-31 May 1996
Firstpage
645
Lastpage
651
Abstract
The objective of this paper is to focus on design considerations and on design methodology for high performance packages. Discussion will be restricted to Single Chip Packages only. Wirebond and Flip chip packages in Pin Grid and Ball Grid I/Os are described here. As shown here design considerations are primarily driven by customer input followed by electrical modeling and process modeling to guarantee performance and cost. The electrical performance of the package is analyzed by evaluating the parasitic parameters
Keywords
design engineering; flip-chip devices; integrated circuit packaging; lead bonding; 50 MHz; ball grid I/Os; cross talk; delta-I noise; design; electrical modeling; electrical performance; flip chip packages; high performance packages; impedance; parasitic parameters; pin grid I/Os; power loop inductance; process modeling; single chip packages; wirebond packages; Boundary conditions; Costs; Delay; Design methodology; Electronics packaging; Flip chip; Frequency; Impedance; Inductance; Performance analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components and Technology Conference, 1996. Proceedings., 46th
Conference_Location
Orlando, FL
ISSN
0569-5503
Print_ISBN
0-7803-3286-5
Type
conf
DOI
10.1109/ECTC.1996.517454
Filename
517454
Link To Document