DocumentCode :
2683253
Title :
ESD qualification and testing of semiconductor electronic components
Author :
Gross, Vaughan P. ; Voldman, Stephen H. ; Guthrie, William H.
Author_Institution :
IBM Microelectron., USA
fYear :
1996
fDate :
28-31 May 1996
Firstpage :
671
Lastpage :
681
Abstract :
Electrostatic discharge (ESD) standards, qualification and testing techniques are not keeping pace with the wide proliferation of product and package types, chip architectures, digital/analog mixed signal applications, multichip module (MCM) packages, and three-dimensional silicon packages. ESD test standards are primarily focused on impulse wave forms and testers and are not addressing the pace and changing trend of the semiconductor industry. For example, most ESD event simulators are not adequately addressing product with high pin counts, high-volume testing, and software needs. This paper discusses our perspective of those adjustments needed to drive ESD learning on product chips and of new package environments. Also discussed are ESD testing methodologies, wafer-level test systems, packaging effects, simulation, and MCM ESD testing
Keywords :
electrostatic discharge; multichip modules; semiconductor device packaging; semiconductor device testing; ESD; chip architectures; digital/analog mixed signal applications; electrostatic discharge; multichip module packages; qualification; semiconductor electronic components; simulation; standards; testing; three-dimensional silicon packages; wafer-level testing; Electronic equipment testing; Electronics packaging; Electrostatic discharge; Impulse testing; Multichip modules; Qualifications; Semiconductor device packaging; Semiconductor device testing; System testing; Wafer scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference, 1996. Proceedings., 46th
Conference_Location :
Orlando, FL
ISSN :
0569-5503
Print_ISBN :
0-7803-3286-5
Type :
conf
DOI :
10.1109/ECTC.1996.517457
Filename :
517457
Link To Document :
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