An MDE approach for modeling network on chip topologies

Network on Chip (NoC) is a research field path that primarily addresses the global communication in System on Chip (SoC).The selected topology of the components interconnects plays a prime role in the performance of NoC architecture, for NoC conception, high-level synthesis approaches are utilized thus the behaviorally description of the system is refined into an accurate register-transfer-level (RTL) design for SoC implementation. In the recent MARTE (Modeling and Analysis of Real-time and Embedded Systems) Profile, a notion of multidimensional multiplicity has been proposed to model repetitive structures and topology. This paper presents a contribution for a new methodology for modeling NoC based Model Driven Architecture and the Modeling and Analysis of Real-Time and embedded System (MARTE), it aims to prove the effectiveness of standard MARTE in modeling irregular or globally irregular locally regular architectures. We will start this work by high level abstraction to reach low level through generated VHDL code.