Title :
A Low Noise AiGaAs/GaAs FET with P/sup +/-Gate and Selectively Doped Structure
Author :
Onata, K. ; Hida, H. ; Miyamoto, H. ; Ogawa, M. ; Baba, T. ; Mizutani, T.
fDate :
May 30 1984-June 1 1984
Abstract :
A low noise AIGaAs/GaAs FET with p/sup +/-gate and selectively doped structure has been developed. The FET utilizing a two dimensional electron gas has a closely spaced electrode planar structure on an MBE wafer. A 0.5 µm gate FET exhibited marked room temperature performances of 310 mS/mm transconductance and 1.2 dB noise figure with 11.7 dB associated gain at 12 GHz.
Keywords :
Contact resistance; Electrodes; Etching; FETs; Fabrication; Gallium arsenide; Ohmic contacts; Resists; Temperature; Transconductance;
Conference_Titel :
Microwave Symposium Digest, 1984 IEEE MTT-S International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/MWSYM.1984.1131820
