• DocumentCode
    2684275
  • Title

    A Low Noise AiGaAs/GaAs FET with P/sup +/-Gate and Selectively Doped Structure

  • Author

    Onata, K. ; Hida, H. ; Miyamoto, H. ; Ogawa, M. ; Baba, T. ; Mizutani, T.

  • fYear
    1984
  • fDate
    May 30 1984-June 1 1984
  • Firstpage
    434
  • Lastpage
    436
  • Abstract
    A low noise AIGaAs/GaAs FET with p/sup +/-gate and selectively doped structure has been developed. The FET utilizing a two dimensional electron gas has a closely spaced electrode planar structure on an MBE wafer. A 0.5 µm gate FET exhibited marked room temperature performances of 310 mS/mm transconductance and 1.2 dB noise figure with 11.7 dB associated gain at 12 GHz.
  • Keywords
    Contact resistance; Electrodes; Etching; FETs; Fabrication; Gallium arsenide; Ohmic contacts; Resists; Temperature; Transconductance;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microwave Symposium Digest, 1984 IEEE MTT-S International
  • Conference_Location
    San Francisco, CA, USA
  • ISSN
    0149-645X
  • Type

    conf

  • DOI
    10.1109/MWSYM.1984.1131820
  • Filename
    1131820
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2684275