A Reconfigurable IF to DC Sub-Sampling Receiver Architecture With Embedded Channel Filtering for 60 GHz Applications

This paper presents the theoretical analysis and simulation results of an IF to DC subsampler for 60 GHz heterodyne receivers architectures. A particular arrangement of the frequency plan allows embedded anti-alias filtering. Down-conversion, channel filtering and IQ demodulation are merged into a unique operation at no extra cost in terms of area and power consumption. The adjacent and alternate channel rejections for the 802.15.3.c are respectively more than 15 dBc and 23 dBc thanks to charge domain subsamplers. This paper presents solutions for the implementation of the system and its integration into a complete 60 GHz receiver. Advanced analysis is made for critical points of the architecture: generation of the integration windows, IQ demodulation, noise folding and effect of clock jitter. The proposed architecture is validated by simulations and complies with the requirements of the standards for 60 GHz wireless communications. The result of this study shows that sub-sampling is suitable for high bandwidth and high data-rate receiver systems.