The application of a dual-substrate technique on a 10-Gb/s CMOS phase detector design

This paper presents a new dual-substrate technique used to overcome the small rail-to-rail supply voltage headroom available for short channel length CMOS technology. The technique is applied on a full-rate CMOS phase detector (PD) for synchronous optical network (SONET) OC-192 systems. A sample-and-hold PD for 10-Gb/s non return zero (NRZ) data implemented in a standard 0.18 μm CMOS technology is presented. The measurement results show that a linear range with no dead zone on phase error from -π/2 to π/2 is achieved. The core circuit dissipates a total power of 14.9mW from a +/- 1.6 V supply.