Title :
Synthesis of Sequential Circuits for Robust Path Delay Fault Testability
Author :
Bhatia, Sandeep ; Jha, Niraj K.
Author_Institution :
Princeton University
Keywords :
Circuit faults; Circuit synthesis; Circuit testing; Combinational circuits; Delay effects; Latches; Logic testing; Robustness; Sequential analysis; Sequential circuits;
Conference_Titel :
VLSI Design, 1993. Proceedings. The Sixth International Conference on
Print_ISBN :
0-8186-3180-5
DOI :
10.1109/ICVD.1993.669696
