Title :
A 14-port 3.8 ns 116-word 64b read-renaming register file
Author :
Asato, C. ; Montoye, R. ; Gmuender, J. ; Wade Simmons, E. ; Ike, A. ; Zasio, J.
Author_Institution :
HaL Comput. Syst. Inc., Campbell, CA, USA
Abstract :
A 116-word/spl times/64b register file with ten read ports and four write ports is part of a four-issue superscalar, register-renamed, four-window, V9 SPARC-architecture CPU operating at 154MHz. Since the register file combines a register-rename function with the register-read operation, the CPU pipeline is one stage shorter than other register-renaming architectures.
Keywords :
file organisation; memory architecture; multiport networks; naming services; pipeline processing; 154 MHz; 3.8 ns; 64 bit; CPU pipeline; read-renaming register file; register-read operation; register-rename function; superscalar four-window V9 SPARC-architecture; Circuits; Clocks; Decoding; Latches; Logic arrays; Pipelines; Pulse amplifiers; Read only memory; Registers; Switches;
Conference_Titel :
Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-2495-1
DOI :
10.1109/ISSCC.1995.535449
