DocumentCode
2685969
Title
A fully symmetrical PFD for fast locking low jitter PLL
Author
Yong-Ming Li ; Hong-yi Chen
Volume
2
fYear
2003
fDate
21-24 Oct. 2003
Firstpage
725
Abstract
A fully symmetrical phase-frequency detector (fs-PFD) is proposed in this paper. Because there is no feedback path in the fs-PDF circuit, it can be operated above 1GHz. Some improvements are made to get a dead zone of only 12 ps. Phase locked loop (PLL) using the fs-PFD has a reduced locking time and an output signal frequency with little jitter.
Keywords
jitter; phase detectors; phase locked loops; circuit feedback; dead zone; fast locking PLL; feedback path; fully symmetrical PFD; fully symmetrical phase-frequency detector; low jitter PLL; output signal frequency; phase locked loop; reduced locking time;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2003. Proceedings. 5th International Conference on
ISSN
1523-553X
Print_ISBN
0-7803-7889-X
Type
conf
DOI
10.1109/ICASIC.2003.1277313
Filename
1277313
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