DocumentCode
2685985
Title
A CMOS PLL using current-adjustable charge-pump and on-chip loop filter with initialization circuit
Author
Zhao Hui ; Ren Junyan ; Zhang Qianling
Author_Institution
ASIC & Syst. State Key Lab., Fudan Univ., Shanghai, China
Volume
2
fYear
2003
fDate
21-24 Oct. 2003
Firstpage
728
Abstract
A 900MHz CMOS PLL using current-adjustable charge-pump circuit and on-chip loop filter with initialization circuit is presented. The charge-pump current is insensitive to the changes of temperature and power supply. The value of the charge-pump current can be changed by switches which are controlled by external signals. Thus the performance of the PLL, such as loop bandwidth, can be changed with the change of the charge-pump current. The loop filter initialization circuit can speed up the PLL when power on. A multi-modulus prescaler is used to fulfill the frequency division in the feedback loop. The circuit is designed in 0.18μm 1.8V 1P6M standard digital CMOS process.
Keywords
CMOS digital integrated circuits; feedback; phase locked loops; prescalers; 0.18 microns; 1.8 V; 900 MHz; CMOS PLL; CMOS process; charge-pump current; current-adjustable charge-pump; feedback loop; loop bandwidth; loop filter initialization circuit; multimodulus prescaler; on-chip loop filter;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2003. Proceedings. 5th International Conference on
ISSN
1523-553X
Print_ISBN
0-7803-7889-X
Type
conf
DOI
10.1109/ICASIC.2003.1277314
Filename
1277314
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