Tracking radar digital matched-filter ASIC design and its error analysis

Matched-filter is widely used in real time signal processing, especially in radar signal processing. This paper presents a novel structure of digital tracking radar matched-filter, whose hardware overhead is one third of traditional design but its throughput is doubled. With block-floating-point arithmetic, the precision is high improved. The whole digital matched-filter is implemented in just one chip of FPGA. This ASIC has two work modes: 512 points pulse compression and 256 points pulse compression. It complements three channels of 512-points complex signal in 102us. The noise-to-signal ratio formula of this matched-filter is deduced at the end of the paper.