Title :
VLSI design of bit-retimed and pipelined recursive filters
Author_Institution :
Thailand IC Design Incubator, Nat. Electron. & Comput. Technol. Center, Nonthaburi, Thailand
Abstract :
This paper suggests a bit-level retime and pipelining (BRP) technique that improves the area-time-power performance of digital recursive filters. The technique is based on the fast bit-retiming technique proposed earlier. The example shows that BRP based filter is 44% smaller, 22% faster and consumes 12% less power than a non-retimed equivalent.
Keywords :
VLSI; pipeline processing; recursive filters; VLSI design; area-time-power performance; bit-level retime; bit-retiming technique; digital recursive filters; pipelined recursive filters; pipelining technique;
Conference_Titel :
ASIC, 2003. Proceedings. 5th International Conference on
Print_ISBN :
0-7803-7889-X
DOI :
10.1109/ICASIC.2003.1277329
