• DocumentCode
    2686223
  • Title

    VLSI design of bit-retimed and pipelined recursive filters

  • Author

    Israsena, P.

  • Author_Institution
    Thailand IC Design Incubator, Nat. Electron. & Comput. Technol. Center, Nonthaburi, Thailand
  • Volume
    2
  • fYear
    2003
  • fDate
    21-24 Oct. 2003
  • Firstpage
    792
  • Abstract
    This paper suggests a bit-level retime and pipelining (BRP) technique that improves the area-time-power performance of digital recursive filters. The technique is based on the fast bit-retiming technique proposed earlier. The example shows that BRP based filter is 44% smaller, 22% faster and consumes 12% less power than a non-retimed equivalent.
  • Keywords
    VLSI; pipeline processing; recursive filters; VLSI design; area-time-power performance; bit-level retime; bit-retiming technique; digital recursive filters; pipelined recursive filters; pipelining technique;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ASIC, 2003. Proceedings. 5th International Conference on
  • ISSN
    1523-553X
  • Print_ISBN
    0-7803-7889-X
  • Type

    conf

  • DOI
    10.1109/ICASIC.2003.1277329
  • Filename
    1277329
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2686223