Title :
Miniaturization design of backside-via structures underneath collector-Up HBTs using A 3-D finite-element model
Author :
Tseng, H.C. ; Lee, P.H. ; Chou, J.H.
Author_Institution :
Nanotechnol. R & D Center, Kun Shan Univ., Tainan
Abstract :
To carry out the miniaturization design of backside-via packaging structures underneath collector-up HBTs, a 3-D finite-element model has been developed for analyzing temperature-distribution phenomena within the configurations. The results are demonstrated on the three-finger InGaP/GaAs collector-up HBT. Compared to previous reports, backside-via structures can be further reduced by 42% while maintaining the same heat-dissipation performance.
Keywords :
III-V semiconductors; finite element analysis; gallium arsenide; heterojunction bipolar transistors; indium compounds; semiconductor device models; semiconductor device packaging; 3D finite element model; InGaP-GaAs; backside via structures underneath collector up HBT; heat dissipation performance; miniaturization design; temperature distribution phenomena; Capacitance; Fingers; Finite element methods; Gallium arsenide; Heterojunction bipolar transistors; Packaging; Temperature distribution; Thermal conductivity; Thermal management; Thermal resistance;
Conference_Titel :
Electronic Packaging Technology & High Density Packaging, 2008. ICEPT-HDP 2008. International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-2739-0
Electronic_ISBN :
978-1-4244-2740-6
DOI :
10.1109/ICEPT.2008.4606986
