A VLSI architecture of EBCOT encoder for JPEG2000

Embedded block coding with optimized truncation (EBCOT) algorithm plays a basic and crucial part in JPEG2000 still image compression system. This paper proposes VLSI architecture of EBCOT, in which a dynamic memory control (DMC) strategy is used to reduce 60% of the on-chip wavelet coefficients storage. A parallel architecture is proposed to speed-up the coding process. This architecture can be used as a compact and efficient IP core for JPEG2000 VLSI implementation and various real-time image and video applications.