A VLSI chip of SCLA based 2-D DWT/IDWT

We have designed a VLSI chip of spatial combinative lifting algorithm (SCLA) based 2-D biorthogonal DWT/IDWT. This DWT/IDWT processor is implemented with 9/7, 5/3 Daubechies filters and 5-level Mallat decomposition method, which can possess 30 frames per second with image resolution up to 1280 × 1024 × 24 bits under 50 MHz system clock. This processor is fabricated with DONGBU 0.25 μm 1P4M standard CMOS technology, with 25k logic gates plus 93k bits on-chip memory and 1.1mW/MHz power consumption, in a 7.84 mm² die size, which can be used as a compact and efficient hard IP core for JPEG2000 codec VLSI implementation and many other real-time video/audio applications.