• DocumentCode
    2686783
  • Title

    A March-CL test for interconnection faults of SOC

  • Author

    Jinyi, Zhang ; Xiaodong, Yang ; Yi, Yang ; Dong, Zhang ; Hui, Dong

  • Author_Institution
    Key Lab. of Adv. Displays & Syst. Applic., Shanghai Univ., Shanghai
  • fYear
    2008
  • fDate
    28-31 July 2008
  • Firstpage
    1
  • Lastpage
    5
  • Abstract
    Shrinks of feature size, high working frequency, and rising number of the IP cores integrated in SOC make the problem with interconnection test critics. A March-CL test for interconnection faults of SOC is proposed in this article. According to the method, eight test patterns are used to detect stuck and delay faults of interconnection between IP cores. The IP connected by interconnection under test (IUT) is wrapped and complied with IEEE1500. Short test time and low area overhead are achieved with the method. Moreover, modified wrapper cell structure with simple control logic is adopted for detecting delay in March-CL test. Finally, March-CL test is applied to ITCpsila02 bench, and result proves that the method covers 100% of stuck, bridge and delay faults in synchronous interconnection test.
  • Keywords
    fault diagnosis; logic testing; system-on-chip; IEEE1500; IP cores; March-CL test; SOC; control logic; delay faults; interconnection faults; interconnection under test; low area overhead; modified wrapper cell structure; short test time; synchronous interconnection test; Bridge circuits; Bridges; Crosstalk; Delay; Fault detection; Frequency; Laboratories; Logic testing; Materials testing; Test pattern generators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Packaging Technology & High Density Packaging, 2008. ICEPT-HDP 2008. International Conference on
  • Conference_Location
    Shanghai
  • Print_ISBN
    978-1-4244-2739-0
  • Electronic_ISBN
    978-1-4244-2740-6
  • Type

    conf

  • DOI
    10.1109/ICEPT.2008.4607018
  • Filename
    4607018