Title :
A pipelined low power architectural MPEG-4 video codec chip with deblocking filter for mobile wireless multimedia applications
Author :
Bontae Koo ; Seongmin Kim ; Seokho Lee ; Minseok Choi ; Kihyuk Park ; Nakwoong Eum ; Jongdae Kim
Author_Institution :
Adv. Micro-Electron. Res. Lab., ETRI, Daejeon, South Korea
Abstract :
We present a low-power MPEG-4 video codec chip capable of delivering high-quality video data in mobile wireless multimedia applications. The discussions focus on the architectural design techniques for implementing a high-performance and low power consumption video compression/decompression chip. By introducing partitioning of HW/SW modules, the efficiently optimized frame memory interface architecture, motion estimation skip scheme, and macroblock based pipeline deblocking filtering scheme, the proposed MPEG-4 video codec has low power consumption for mobile wireless multimedia application such as mobile phone, PDA and DMB. The proposed MPEG-4 video codec can perform 30 frames/s of QCIF or 7.5 frame/s of CIF at 27MHz with 128k-144kbps rates. Power consumption is 290mW and the chip size is 9.7mm × 9.7mm at 0.35 μm CMOS technology.
Keywords :
CMOS integrated circuits; codecs; digital signal processing chips; low-power electronics; mobile communication; multimedia communication; pipeline arithmetic; 0.35 microns; 128 to 144 kbit/s; 27 MHz; 290 mW; CMOS technology; DMB; HW modules; PDA; SW modules; architectural design techniques; deblocking filter; frame memory interface architecture; high-quality video data; low power consumption; low-power MPEG-4 video codec chip; mobile phone; mobile wireless multimedia applications; motion estimation skip scheme; pipeline deblocking filtering scheme; pipelined low power architecture; video compression chip; video decompression chip;
Conference_Titel :
ASIC, 2003. Proceedings. 5th International Conference on
Print_ISBN :
0-7803-7889-X
DOI :
10.1109/ICASIC.2003.1277364
