A novel SAD computing hardware architecture for variable-size block motion estimation and its implementation with FPGA

Author

Cao Wei ; Mao Zhi Gang

Author_Institution

Microelectron. Center, Harbin Inst. of Technol., China

Volume

2

fYear

2003

fDate

21-24 Oct. 2003

Firstpage

950

Abstract

This paper presents a new hardware architecture that calculates SAD for variable block-size motion estimation (VBSME). The proposed architecture with a 16×1-PE array, a 4-stage adder tree and two flexible register arrays supports 16×16, 16×8, 8×8, 8×4, 4×8, and 4×4 block´s SAD calculation. The architecture can be used in the encoder that supports the enhanced motion estimation with variable block size in the MPEG-4 AVC (advanced video coding) and the emerging H.264 standard. Our design was described in Verilog-HDL and implemented in a Altera FPGA APEX20K with a clock frequency of 120MHz allowing the processing of 29296 16×16 per search area.

Keywords

digital signal processing chips; field programmable gate arrays; motion estimation; video signal processing; 120 MHz; Altera APEX20K; FPGA; H.264 standard; MPEG-4 AVC; SAD computing hardware architecture; VBSME; Verilog-HDL; adder tree; advanced video coding; field programmable gate array; register arrays; variable block size; variable-size block motion estimation;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2003. Proceedings. 5th International Conference on

ISSN

1523-553X

Print_ISBN

0-7803-7889-X

Type

conf

DOI

10.1109/ICASIC.2003.1277368

Filename

1277368