A general architecture for zerotree encoder

This paper presents a general zerotree encoder architecture based on parallel processing of multi-bit-planes and two-stage encoder and EZW encoder. The parallel processing of multi-bit-planes is supported with a simple preprocess unit pipelined in encoding process. The two-stage encoding technique reduces the recursive processing significantly by partitioning the encoding process into two orderly scans. Additionally, a simplified encoder based on the MPEG-4 zerotree encoder is proposed that employs the clearing processing in place of the skip processing. The compression performance changes a little and becomes slightly better when PSNR is below 37dB around. Using the technique can save more than 20% both circuit resource and computation time than the MPEG-4 zerotree encoder.