VSPEC constraints modeling and evaluation

Author

Rajkhowa, Amitvikram ; Alexander, Perry

Author_Institution

Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA

fYear

1999

fDate

7-12 Mar 1999

Firstpage

159

Lastpage

165

Abstract

Performance constraints play a key role in VLSI design. Performance constraints evaluation help in discovering requirements specification errors at an early stage in the design process when they are easy to fix. VSPEC is a requirements specification language for digital systems that contains a standard method for describing constraints. The paper presents a method of evaluating and verifying these constraints. Performance Description Language (PDL) is used for evaluation. The system is implemented within the ORBIT design environment

Keywords

VLSI; formal specification; high level synthesis; specification languages; ORBIT design environment; PDL; Performance Description Language; VLSI design; VSPEC constraints modeling; design process; digital systems; performance constraints; requirements specification errors; requirements specification language; standard method; Aging; Circuits; Computer Society; Hardware; IEEE services; Power dissipation; System analysis and design; Timing; USA Councils; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Engineering of Computer-Based Systems, 1999. Proceedings. ECBS '99. IEEE Conference and Workshop on

Conference_Location

Nashville, TN

Print_ISBN

0-7695-0028-5

Type

conf

DOI

10.1109/ECBS.1999.755875

Filename

755875