Title :
A Shared Memory Parallel Algorithm for Logic Synthesis
Author :
Lim, Chieng-Fai ; Banerjee, Prithviraj ; De, Kaushik ; Muroga, Saburo
Author_Institution :
Coordinated Science Lab
Keywords :
Aerodynamics; Circuit synthesis; Load management; Logic functions; Minimization methods; Network synthesis; Optimization methods; Parallel algorithms; Programmable logic arrays; Terminology;
Conference_Titel :
VLSI Design, 1993. Proceedings. The Sixth International Conference on
Print_ISBN :
0-8186-3180-5
DOI :
10.1109/ICVD.1993.669703
