Title :
A 5.8-GHz delta-sigma fractional-N frequency synthesizer for IEEE 802.11a applications
Author :
Sau-Mou Wu ; Ron-Yi Liu ; Wei-Liang Chen
Author_Institution :
Graduate Sch. of Electr. Eng., Yuan Ze Univ., Chungli, Taiwan
Abstract :
A 5.8-GHz fractional-N frequency synthesizer for IEEE 802.11a WLAN applications is designed in a 0.25μm CMOS process. The synthesizer integrates a low power, high efficient voltage-controlled oscillator (VCO), an injection-locked frequency divider and a digital third-order MASH delta-sigma modulator together. The VCO is capable of 240MHz tuning range and exhibits a phase noise of about -115dBc/Hz at 1MHz offset from the center frequency throughout the tuning range. The synthesizer has a bandwidth of 300KHz for a 35MHz reference and can achieve a close-in phase noise of about -80dBc/Hz while the total power consumption is 35mW from a single 2.5V supply.
Keywords :
CMOS integrated circuits; delta-sigma modulation; frequency synthesizers; low-power electronics; phase noise; voltage-controlled oscillators; wireless LAN; 0.25 microns; 1 MHz; 2.5 V; 240 MHz; 300 KHz; 35 MHz; 35 mW; 5.8 GHz; CMOS process; IEEE 802.11a applications; VCO; WLAN applications; delta-sigma frequency synthesizer; digital third-order MASH delta-sigma modulator; fractional-N frequency synthesizer; injection-locked frequency divider; phase noise; voltage-controlled oscillator;
Conference_Titel :
ASIC, 2003. Proceedings. 5th International Conference on
Print_ISBN :
0-7803-7889-X
DOI :
10.1109/ICASIC.2003.1277398
