A special purpose coprocessor supporting cell placement and floorplanning algorithms

A coprocessor supporting a variety of placement and floorplanning algorithms is described. Without special hardware, the CPU time used by placement algorithms for net length computations can reach up to about 50% of the total run time. The proposed coprocessor architecture has special provisions for efficient net length computation which also allow concurrent execution with the main CPU. A prototype chip has been manufactured. The estimated speedup factor is about 40 for wire-length calculations. The chip can easily be integrated into current computer systems and usually requires only minimal changes to existing placement programs