DocumentCode
2687437
Title
A hierarchical floor-planning, placement, and routing tool for sea-of-gates designs
Author
Ng, Charles ; Ashtaputre, Sunil ; Chambers, Elizabeth ; Do, Kieu-huong ; Hui, Siu-tong ; Mody, Rajiv ; Wong, Dale
fYear
1989
fDate
15-18 May 1989
Abstract
The authors present an automatic layout system for designing large sea-of-gates gate arrays. This tool combines a floorplanning tool with an automatic placement and routing tool. It is designed to handle 250 K-gate arrays with special functional blocks such as RAM and ROM. It provides features for current processing, timing-driven layout, special clock distribution, and power distribution. The tool is currently being tested for designing the industry´s most complex sea-of-gates gate arrays
Keywords
cellular arrays; circuit layout CAD; logic CAD; logic arrays; CAD; RAM; ROM; automatic layout system; automatic placement; computer aided design; current processing; floorplanning tool; gate arrays; hierarchical floor-planning; logic arrays; power distribution; routing tool; sea-of-gates designs; special clock distribution; special functional blocks; timing-driven layout;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1989., Proceedings of the IEEE 1989
Conference_Location
San Diego, CA, USA
Type
conf
DOI
10.1109/CICC.1989.56680
Filename
5726149
Link To Document