Title :
Layout optimization of spiral inductors in silicon chip for 5.7GHz WLAN
Author_Institution :
Inst. of Microelectron., Singapore, Singapore
Abstract :
A process to design and optimize the layout structure of inductors has been proposed. A set of inductors working at 5.7 GHz for WLAN has been designed based on using low resistivity silicon substrates and the 0.18 μm Cu/SiO2 interconnect technology. The layout structures such as the inner core size, coil-width and coil-space of the inductors (0.2 nH to 11 nH) have been optimized. The optimized Q-value at 5.7 GHz is improved by a factor of 5 - 8 as compared to the tested Q-value of inductors using previous layout.
Keywords :
Q-factor; circuit optimisation; inductors; integrated circuit layout; silicon compounds; wireless LAN; 0.18 microns; 5.7 GHz; Cu-SiO2; Q-value; WLAN; coil space; coil width; inductor layout structure; inner core size; interconnect technology; layout optimization; layout structures; low resistivity silicon substrates; silicon chip; spiral inductors;
Conference_Titel :
ASIC, 2003. Proceedings. 5th International Conference on
Print_ISBN :
0-7803-7889-X
DOI :
10.1109/ICASIC.2003.1277401
