Abstract :
The author describes a logic optimization system that serves as the workhorse for three high level and one RTL-level synthesis systems. LOGOPT is capable of combinational and limited sequential circuit optimization and is particularly useful for resynthesis of netlists. The author describes the process of resynthesis with an effective approach to netlist partitioning for selective retention of hierarchy. This technique is invaluable for high-level synthesis and can also be used for partitioning existing netlists, so that troublesome or structured functions, such as arithmetic functions, can be efficiently implemented, either manually or with structured synthesis techniques. LOGOPT can optimize the glue-logic, while also performing netlist-netlist verification and timing optimization. Netlist-netlist verification coupled with the netlist partitioning can be used for verification of incremental changes, thus avoiding the need for simulation. The architecture of LOGOPT is described, and experimental data on the use of LOGOPT over a spectrum of actual designs is presented
Keywords :
combinatorial circuits; logic CAD; optimisation; sequential circuits; CAD; LOGOPT; RTL-level synthesis; arithmetic functions; combinational circuits; high-level synthesis; logic optimization system; multi-level logic synthesis; netlist partitioning; netlist-netlist verification; netlists resynthesis; sequential circuit; structured functions; structured synthesis techniques; timing optimization;