DocumentCode :
2687644
Title :
Characterization and optimization of defects and defect tolerance for not-practically-testable circuits
Author :
Patitz, X. ; George, K.M. ; Park, N. ; Kim, E. -K
Author_Institution :
Dept. of Comput. Sci., Oklahoma State Univ. Stillwater, Stillwater, OK, USA
fYear :
2010
fDate :
3-6 May 2010
Firstpage :
754
Lastpage :
759
Abstract :
The aim of the work is ultimately to establish a theoretical foundation for economical decision making on whether to test; how far to test; whether testing is feasible; and, otherwise, whether there is an alternative to defect tolerance with little or no testing. In this work, a new defect tolerance for the circuits and systems under the circumstances where little or no testing is allowed or feasible, is to be investigated. New methodologies for the design for defect tolerance will be presented and theoretically validated.
Keywords :
integrated circuit testing; tolerance analysis; defect tolerance; not practically testable circuits; quality level; Circuit testing; Circuits and systems; Computer science; Decision making; Design methodology; Geometry; Manufacturing; Robustness; System testing; Wires; Defect level; defect tolerance; quality level; testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Instrumentation and Measurement Technology Conference (I2MTC), 2010 IEEE
Conference_Location :
Austin, TX
ISSN :
1091-5281
Print_ISBN :
978-1-4244-2832-8
Electronic_ISBN :
1091-5281
Type :
conf
DOI :
10.1109/IMTC.2010.5488115
Filename :
5488115
Link To Document :
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