A 12 ns, CMOS programmable logic device for combinatorial applications

Author

Gowni, Shiva P. ; Platt, Paul E. ; Hawkins, Andrew L. ; Hiltpold, W. Randolph ; Douglass, Steve M.

fYear

1989

fDate

15-18 May 1989

Abstract

A 12-ns, 400-mW programmable logic device implemented in two-layer metal, 0.8-μm CMOS EPROM technology is presented. The device is optimized for combinatorial applications and provides programmable input macrocells for latched, registered, or combinatorial inputs. This device provides 1200 equivalent gates in a 28-pin package, with 13 inputs, 12 I/Os, one VCC, and two VSS pins. Each I/O pin, in addition to the programmable input register, has a product-term-controlled XOR gate for dynamic output polarity control and a control mux for output enable. The part has selective, nonvolatile power-down of unused circuitry. The sense amplifier is optimized for speed and power and is compensated for process, temperature, and pattern variations. The device uses a regulated substrate bias generator optimized for the process to improve latchup immunity and performance

Keywords

CMOS integrated circuits; EPROM; cellular arrays; combinatorial circuits; logic arrays; 0.8 micron; 12 ns; 28-pin package; 400 mW; CMOS EPROM technology; combinatorial applications; control mux; dynamic output polarity control; latched inputs; latchup immunity; output enable; product-term-controlled XOR gate; programmable input macrocells; programmable input register; programmable logic device; registered inputs; regulated substrate bias generator; selective nonvolatile power-down capability; sense amplifier; two-layer metal;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1989., Proceedings of the IEEE 1989

Conference_Location

San Diego, CA, USA

Type

conf

DOI

10.1109/CICC.1989.56694

Filename

5726163