Test scheduling for system-on-a-chip using test resource grouping

Test scheduling has been known to be one of the efficient techniques for reducing testing time of system-on-a-chip (SoC). In this paper, a heuristic algorithm, in which test resources are grouped and arranged, based on the size of product of power dissipation and test time of each core together with total power consumption in core-based SoC is proposed. We select test resource groups which have maximum power consumption but do not exceed the constrained power consumption and make the testing time slot of resources aligned at the initial position to time slot of resources aligned at the initial position to minimize the idling test time of test resources.