A new BIST structure for low power testing

A new simple built-in-self-test (BIST) structure for low power testing is presented in this paper. The principle of the proposed method is to reconstruct the LFSR circuit to reduce the WSA of the circuit under test (CUT) by choosing the CUT´s heavy inputs. Experimental results shows that it can efficiently reduce the number of transitions in the CUT; hence decrease the total power consumption during testing. Moreover, these results are obtained with no loss of stuck-at-fault coverage (FC).