Title :
A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme
Author :
Kang-Deog Suh ; Byung-Hoon Suh ; Young-Ho Um ; Jin-Ki Kim ; Young-Joon Choi ; Yong-Nam Koh ; Sung-Soo Lee ; Suk-Chon Kwon ; Byung-Soon Choi ; Jin-Sun Yum ; Jung-Hyuk Choi ; Jang-Rae Kim ; Hyung-Kyu Lim
Author_Institution :
Samsung Electron. Co. Ltd., Kiheung, South Korea
Abstract :
Due to their small cell size, low power consumption, and fast page based read/program operations, NAND type flash memories are well suited for portable mass storage. This 3.3 V only 32 Mb NAND flash memory achieves typical 2.3 MB/s program performance with an incremental step pulse programming (ISPP) scheme. In addition, self-boosting of program inhibit voltages lowers the page programming current to 4.3 mA and a 24 MB/s read throughput is achieved with interleaved data paths. The device is fabricated in a 0.5 /spl mu/m CMOS process on a 94.9 mm/sup 2/ die.
Keywords :
CMOS memory circuits; 0.5 micron; 3.3 V; 32 Mbit; 4.3 mA; CMOS process; EEPROM; NAND flash memory; incremental step pulse programming scheme; interleaved data paths; low power consumption; page based read/program operations; program inhibit voltages; self-boosting; CMOS process; Capacitance; Decoding; Energy consumption; Flash memory; Interference; Latches; Ocean temperature; Space vector pulse width modulation; Voltage control;
Conference_Titel :
Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-2495-1
DOI :
10.1109/ISSCC.1995.535460
