DocumentCode :
2688037
Title :
0.8 μm 1.4 MTr. CMOS SOG based on column macro-cell
Author :
Okuno, Yoshihiro ; Okabe, Masatomi ; Arakawa, Takahiko ; Tomioka, Ichiro ; Ohno, Takio ; Noda, Tomoyoshi ; Kuramitsu, Yoichi
fYear :
1989
fDate :
15-18 May 1989
Abstract :
Column macro-cell architecture has been verified to be advantageous for increasing silicon utilization in experimental circuit layouts. As an application, a 64-b multiplier with 32-kb RAM and 65-kb ROM using a 1.4-M transistor sea of gates (SOG) has been developed, using 0.8-μm two-layer-metal CMOS. Gate density of 1.5 kg/mm2 and bit densities of 1.9 kb/mm2 for RAM and 6.3/mm2 for ROM have been achieved
Keywords :
CMOS integrated circuits; logic arrays; random-access storage; read-only storage; 0.8 micron; 32 Kbit; 64 bits; 65 Kbit; RAM; ROM; bit densities; column macro-cell; multiplier; sea of gates; silicon utilization; two-layer-metal CMOS;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Custom Integrated Circuits Conference, 1989., Proceedings of the IEEE 1989
Conference_Location :
San Diego, CA, USA
Type :
conf
DOI :
10.1109/CICC.1989.56716
Filename :
5726183
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2688037
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