Minimum leakage pattern generation using stack effect

Leakage power has become a more and more significant issue of VLSI industry as technology scales. Input vector control is an efficient method to reduce leakage current when a circuit operating in standby mode and can be widely used because of its easy implementation and little influence on the original circuit. Fast simulators are urgently needed to generate minimum leakage pattern (MLP), which can be applied to the circuit to suppress the leakage current. Precise circuit simulators (such as HSPICE) can accurately account for leakage power estimation, but are only practical for small circuits. In this paper, a new gate-level leakage power model is introduced considering stack effect to generate MLP. Experiments show MLP method is efficient and applicable for the designs of low leakage and high performance circuits with low timing and area overhead.