Via design optimisation for high speed device packaging

This paper presents the design and electrical characterization of a circular via hole applied to single and multi chip modules. A typical strip line-to-strip line configuration incorporating the via hole is designed, modelled and simulated using the Maxwell Strata mixed potential integration equation (MPIE)-based field solver. This configuration is modelled on a practical user-defined transmission line structure consisting of conductors of finite conductivity. We investigated the effects of three critical parameters, via hole diameter, ground plane opening and via height, on the frequency response. It is found that the via hole diameter should be minimized while the other two parameters should be maximized for better performance. This paper thus provides useful optimization criteria for circular vias, given the practical limitations of manufacturing technologies