Title :
A pipelined multiplication unit
Author :
He Jing ; Han Yue-Qiu
Author_Institution :
Dept. of Electron. Eng., Beijing Inst. of Technol., China
Abstract :
A multiplication unit is described in this paper. The unit can perform 16-bit, 32-bit, single precision and double precision multiplication. BOOTH 2 encoding is used, and 54-bit multiplier is partitioned into multiple sub-multipliers that can operate either as an independent multiplier or as a part of a larger one, so that average latency is reduced and the hardware cost is reduced. Inside each small multiplier, BOOTH 2 encoding is optimized and 4:2 compressors are used to improve the performance. The design is synthesized, implemented and verified with FPGA, and can operate at 25 MHz. The unit is used in the design of a DSP processor.
Keywords :
digital signal processing chips; field programmable gate arrays; multiplying circuits; pipeline arithmetic; 16 bit; 25 MHz; 32 bit; 54 bit; 54-bit multiplier; BOOTH 2 encoding; DSP processor; FPGA; field programmable gate arrays; floating point multiplication; hardware cost; multiple submultipliers; pipelined multiplication unit; precision multiplication;
Conference_Titel :
ASIC, 2003. Proceedings. 5th International Conference on
Print_ISBN :
0-7803-7889-X
DOI :
10.1109/ICASIC.2003.1277441
