• DocumentCode
    2688113
  • Title

    A novel divider based on dual-bit algorithm

  • Author

    Xia Li ; Qianling Zhang

  • Author_Institution
    ASIC & Statge Key Lab, Fudan Univ., Shanghai, China
  • Volume
    2
  • fYear
    2003
  • fDate
    21-24 Oct. 2003
  • Firstpage
    1256
  • Abstract
    The divider is one of the most important modules in microprocessor. A novel divider based on dual-bit algorithm and the VLSI implementation is presented. Compared with the divider of MIPS microprocessor, it decreases the average executing cycles by 57.5%, while its maximum delay is almost the same and its transistor count increases by 60%. The theoretical calculation indicates that the power consumption decreases to 12.3% with the equal operation ability.
  • Keywords
    VLSI; dividing circuits; logic design; microprocessor chips; MIPS microprocessor; VLSI implementation; delay; divider; dual-bit algorithm; power consumption; theoretical calculation; transistor count;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ASIC, 2003. Proceedings. 5th International Conference on
  • ISSN
    1523-553X
  • Print_ISBN
    0-7803-7889-X
  • Type

    conf

  • DOI
    10.1109/ICASIC.2003.1277443
  • Filename
    1277443
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2688113