A 35 ns-cycle-time 3.3 V-only 32 Mb NAND flash EEPROM

Author

Imamiya, K. ; Iwata, Yoshiyuki ; Sugiura, Y. ; Nakamura, H. ; Oodaira, H. ; Momodomi, M. ; Ito, Y. ; Watanabe, T. ; Araki, H. ; Narita, K. ; Masuda, K. ; Miyamoto, Jun

Author_Institution

Semicond. Device Eng. Lab., Toshiba Corp., Kawasaki, Japan

fYear

1995

fDate

15-17 Feb. 1995

Firstpage

130

Lastpage

131

Abstract

A 32 Mb NAND type flash EEPROM in 0.425 /spl mu/m CMOS achieves 35 ns cycle time for data read-out and programming data load by adopting a pipeline scheme. Metal-strapped select gates and boosted word line reduce read-out access time. Tight-programmed cell Vth distribution can be realized by program verify, using a simplified data register circuit. Multiple blocks can be erased at the same time by adopting erase block registers for each block. Simultaneous-erase verify for one block reduces total erase time. All funtions require only 3.3 V power supply.

Keywords

EPROM; 0.425 micron; 3.3 V; 32 Mbit; 35 ns; CMOS; NAND flash EEPROM; boosted word line; cycle time; data read-out access time; data register circuit; erase block registers; metal-strapped select gate; pipeline processing; program verify; simultaneous-erase verify; tight-programmed cell threshold voltage distribution; Circuits; Delay effects; EPROM; Indium tin oxide; Pipelines; Power supplies; Registers; Semiconductor devices; Timing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-2495-1

Type

conf

DOI

10.1109/ISSCC.1995.535461

Filename

535461