A design of regularized multiplier generator

Multiplier is an essential part in processors. Designing it in good performance always costs a long time. A regularized multiplier generator is proposed, which can produce the source codes in VHDL automatically. It can meet the need to shorten the design time. The generator chooses the 4-2 trees, which achieve the same speed performance as equivalent Wallace trees in many cases, but require a simple and regular interconnection scheme. In order to simplify the design work, the regular structure is brought forward. Designers can reuse the optimized sub-circuits as modules. The performances of generated multipliers are comparative to those designed for fixed widths. Some performances of 2´s complement parallel multiplier are analyzed as an illustration.