Title :
A high-performance 32-bit parallel multiplier using modified Booth´s algorithm and sign-deduction algorithm
Author :
Na Tang ; Jian-hui Jiang ; Lin, Kai-Chun
Author_Institution :
R&D Center of VLSI Circuits, Tongji Univ., Shanghai, China
Abstract :
A high-performance 32-bit parallel multiplier is proposed in this paper. A modified Booth´s algorithm is used to unify signed/unsigned numbers operation and a new sign-deduction algorithm is used to eliminate the sign bits array of partial products. This multiplier is used in a 400MHz high performance and full-custom designed 32-bit embedded microprocessor compatible with MIPS 32 4 KC developed by us.
Keywords :
logic design; multiplying circuits; parallel processing; 32 bit; 400 MHz; MIPS 32 4 KC; embedded microprocessor; modified Booth algorithm; parallel multiplier; partial products; sign bits array; sign-deduction algorithm; signed numbers operation; unsigned numbers operation;
Conference_Titel :
ASIC, 2003. Proceedings. 5th International Conference on
Print_ISBN :
0-7803-7889-X
DOI :
10.1109/ICASIC.2003.1277450
