• DocumentCode
    2688263
  • Title

    CMOS high speed digital datastrobe processor

  • Author

    Komatsu, Tatsuya ; Watanab, Kazuo ; Minamimura, Eiji ; Kowase, Yasuaki ; Ueda, Seiichi ; Horie, Noboru ; Asai, Shohjiro ; Matsuura, Tatsuji

  • fYear
    1989
  • fDate
    15-18 May 1989
  • Abstract
    A 1.3-μm CMOS high-speed digital datastrobe processor (DDP) is described. This device uses a high-speed (15 MS/s) 7-bit half-flash analog-to-digital converter, a digital wave equalizer, and a digital phase-locked loop. The DDP has 27 K transistors in a 4.75×4.90 mm 2 chip size and consumes 100 mW
  • Keywords
    CMOS integrated circuits; analogue-digital conversion; digital signal processing chips; phase-locked loops; wave digital filters; 1.3 micron; 100 mW; 15 MHz; 4.75 to 4.9 mm; 7 bit; CMOS; digital datastrobe processor; digital phase-locked loop; digital wave equalizer; half-flash analog-to-digital converter; power dissipation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 1989., Proceedings of the IEEE 1989
  • Conference_Location
    San Diego, CA, USA
  • Type

    conf

  • DOI
    10.1109/CICC.1989.56731
  • Filename
    5726198
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2688263