A multilevel-cell 32 Mb flash memory

Author

Bauer, M. ; Alexis, R. ; Atwood, G. ; Baltar, B. ; Fazio, A. ; Frary, K. ; Hensel, M. ; Ishac, M. ; Javanifard, J. ; Landgraf, M. ; Leak, D. ; Loe, K. ; Mills, D. ; Ruby, P. ; Rozman, R. ; Sweha, S. ; Talreja, S. ; Wojciechowski, Kenneth

Author_Institution

Intel Corp., Folsom, CA, USA

fYear

1995

fDate

15-17 Feb. 1995

Firstpage

132

Lastpage

133

Abstract

A flash memory with multilevel cell significantly reduces the memory per-bit cost. A 32 Mb multilevel-cell (MLC) flash memory storing two bits of data per cell achieves 32 Mb memory storage capacity using 16 M flash memory cells. This 32 Mb flash memory on a 0.6 /spl mu/m process has a 2.0/spl times/1.8 /spl mu/m/sup 2/ flash cell. In MLC operation, the logical flash memory cell achieves two bits per cell using four possible states, defined by four flash cell threshold voltage ranges. The relationship between the threshold voltage ranges stored in the flash memory cell and the corresponding logic levels is shown in this paper, which also shows a plot of the four threshold voltage distributions, each with a separation range.

Keywords

multivalued logic circuits; 0.6 micron; 32 Mbit; logic levels; multilevel-cell flash memory; threshold voltages; Circuits; Flash memory; Flash memory cells; Java; Latches; Logic; Milling machines; Power amplifiers; Pulse amplifiers; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-2495-1

Type

conf

DOI

10.1109/ISSCC.1995.535462

Filename

535462