FPGA implementation of SHA-1 algorithm

In information security, message authentication is an essential technique to verify that received messages come from the alleged source and have not been altered. A key element of authentication schemes is the use of a message authentication code (MAC). One technique to produce a MAC is based on using a hash function and is referred to as an HMAC. Secure Hash Algorithm 1 (SHA-1) is one of the algorithms, which has been specified for use in Internet Protocol Security (IPSEC), as the basis for an HMAC. As we shall show in the paper, it is reasonable to construct cryptographic accelerators using hardware implementations based on SHA-1 hash algorithm. Finally, the synthesis results based on the FPGAs are given.