Title :
A four-processor building block for SIMD processor arrays
Author :
Fisher, Allan L. ; Highnam, Peter T. ; Rockoff, Todd E.
Abstract :
A four-processor chip, for use in processor arrays for image computations, is described. The full-custom 2-μm CMOS chip contains 56669 transistors and runs instructions at 10 MHz. 512 16-bit processors and external memory fit on two industry standard cards to yield 5-GIPS (billions of instructions/s) peak throughput
Keywords :
CMOS integrated circuits; VLSI; computerised picture processing; digital signal processing chips; parallel processing; 10 MHz; 16 bit; 16-bit processors; 2 micron; 5 GIPS; CMOS chip; SIMD processor arrays; external memory; four-processor building block; four-processor chip; image computations; industry standard cards; throughput;
Conference_Titel :
Custom Integrated Circuits Conference, 1989., Proceedings of the IEEE 1989
Conference_Location :
San Diego, CA, USA
DOI :
10.1109/CICC.1989.56739
